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Recurrent Deep Differentiable Logic Gate Networks
Simon Bührer, et al., EdgeFM @ ICML / ICLR 2026 workshop track, August 2025
Abstract
The first recurrent network built from differentiable logic gates, which extends learnable Boolean computation to sequence-to-sequence tasks. On WMT'14 English to German it reaches 5.00 BLEU during training, close to a GRU baseline at 5.41, and drops to 4.39 BLEU once the gates are discretised to hard logic for inference. The goal is sequence models that map directly onto logic hardware.
Tags
- Recurrent Models
- Differentiable Logic
- FPGA Acceleration
- Sequence-to-Sequence
- Edge ML