All papers
BitLogic: A Training Framework for Gradient-Based FPGA-Native Neural Networks
Simon Bührer, et al., TMLR, February 2026
Abstract
An end-to-end, gradient-based framework for training neural networks that run natively on FPGA lookup tables, replacing multiply-accumulate arithmetic with differentiable LUT nodes that use binary computation and sparse connectivity. It comes with modular PyTorch APIs and hardware-aware components, and it exports trained models to synthesisable RTL with verified bit-accurate equivalence. On CIFAR-10 it reaches 72.3% accuracy using under 0.3M logic gates, with single-sample latency below 20 ns.
Tags
- FPGA-Native ML
- Hardware-Aware Training
- Differentiable Logic
- RTL HDL Generation
- PyTorch
- Low-Latency Inference